1. Field of the Invention
This invention relates to a substrate for a semiconductor device, a semiconductor device using the substrate, and a method for the manufacture of the semiconductor device, and more particularly to a substrate for a semiconductor device fit for the construction of a thin semiconductor package of a one-sided seal type, a semiconductor device using the substrate, and a method for the manufacture of the semiconductor device.
2. Description of the Related Art
In the construction of various memory cards, since the cards are restricted by top size and thickness, the semiconductor devices (or semiconductor packages) that contribute to such factors as the memory function are being demanded to be produced in a decreased standard thickness. These semiconductors, at the same time, are demanded to equal roughly the semiconductor elements (semiconductor chips) in size and enjoy compactness.
Such measures as the flip chip packaging method and the chip on board (COB) method have been heretofore known to fulfill the demand for thin layer packaging in the construction of memory cards, specifically the necessity for packaging the cards in a space of not more than 1 mm, for example, in the direction of thickness. As respects the thin semiconductor packages, those which have mutually different essential components laid out as shown in cross section in FIG. 5 and FIG. 6 have been known in the art.
In FIG. 5 and FIG. 6, 1 stands for a substrate provided on one main surface thereof a wiring circuit 1a including a connection part, 2a and 2b for semiconductor chips (flip chips) mounted and packaged on the main surface of the substrate 1, 3 for an external connection terminal led out to the other main surface side of the substrate 1 via a through hole (through-hole junction) 4, and 5 for a sealing resin layer for sealing such an area as intervenes between the semiconductor chips 2a, 2b and the surface of the substrate 1. This substrate 1 uses for an insulator therefor a glass fiber-reinforced resin like a glass-epoxy resin or a ceramic like alumina or aluminum nitride. In FIG. 5 and FIG. 6, 6 stands for a bonding wire for electrically connecting the junction part of the wiring circuit 1a mentioned above to electrode terminals on the surfaces of the semiconductor chips 2a, 2b, and 7 for an adhesive agent layer for attaching fast the semiconductor chips 2a, 2b to predetermined areas of the substrate 1.
The semiconductor device of the one-sided resin seal type shown in FIG. 5 and FIG. 6 is generally manufactured as follows.
As shown in FIG. 7 which depicts essential components in cross section, a lower metallic mold 8 which is provided with a plunger 8a for setting in place and supplying a resin tablet 5a, for example, and a depressed part 8b for setting in place and disposing an assembling substrate 9 and an upper metallic mold 10 which is matched to the lower metallic mold 8 and provided with a depressed part 10b for setting in place and disposing the assembling substrate 9 and a runner part 10a for supplying the melt of the resin tablet 5a are prepared. The depressed part 8b of the lower metallic mold 8 and the depressed part 10b of the upper metallic mold 10 jointly form a so-called cavity.
Then, the assembling substrate 9 having necessary semiconductor chips 2a, 2b set in place and packaged on one main surface of the substrate 1 is set in place and disposed in the depressed part 8b of the lower metallic mold 8. Meanwhile, the tablet 5a of such a thermosetting resin as, for example, epoxy resin is set in place. Subsequently, the upper metallic mold 10 is set in place as aligned with the lower metallic mold 8 having the assembling substrate 9 set in place and disposed thereon to establish a setup for carrying out transfer mold. The thermosetting resin tablet 5a mentioned above is thermally softened and introduced via the runner part 10a and a gate part 10c into the cavity (8b, 10b). After the sealing resin has been supplied to one surface side of the assembling substrate 9 as described above, the sealing resin so supplied is allowed to harden. Thereafter, the metallic molds 8, 10 are separated to obtain such a package body as shown in cross section in FIG. 8.
In FIG. 8, 5' stands for the hardened resin layer in the area corresponding to the runner part 10a and the plunger 8a which extend outwardly from the gate part 10c. This hardened excess resin layer is cut off in the gate part 10c by being folded and rotated near a point 10d at which the end face part of the substrate abuts the hardened resin layer 5'. For the sake of simplicity of description, the mode of manufacturing one package body is depicted here by way of illustrations Generally, the metallic molds mentioned above are so constructed that a plurality of assembling substrates 9 may be set in place and disposed in one plane, with one plunger 8a connected to a plurality of runner parts 10a.
The one-sided mold semiconductor package constructed as described above indeed is at an advantage in safely tolerating the so-called "burn in" test to be performed for the purpose of detecting a defect which would be inherently manifested as a semiconductor chip in the near future before the package is set in place and packaged on a circuit substrate. It nevertheless incurs frequently the following problem. When the sealing resin layer 5 and the excess resin layer 5' are to be cut and separated after the transfer mold mentioned above, they are not broken at the gate part 10c as expected because the sealing resin layer 5 and the excess resin layer 5' manifest high adhesive strength to the surface of the substrate 1. If the separation is forced at all, it often occurs that the sealing resin layer 5 will peel or the substrate 1 will sustain damage or the breakage will occur halfway in the entire length of the runner part 10a.
The peel of the sealing resin layer 5 or the damage of the substrate 1 implies that the reliability of product is at stake and the yield and the automatic productivity are jeopardized. The breakage of the excess resin layer 5' at a point halfway in the entire length of the runner part 10a not only impairs the appearance and dimensional accuracy of the one-sided mold semiconductor package (semiconductor device) but also induces infliction of damage on the substrate 1 and lowers the yield.